MILITARY & AEROSPACE A Wide Dynamic Range Radar Digitizer

W ith the advent of high-speed, high-resolution ana-log to digital converters (ADCs) and associated digital to analog converters (DACs), there is a growing push to move more functionality into the digital signal processing arena. Receiver processing that has been performed in the analog and radio frequency (RF) domains is performed digitally now, with improved performance (near ideal filters and associated signal processing functions) as well as the flexibility to dynamically configure the channel characteristics (i.e., modulation and matched filter response). However, converting from the analog to digital domain introduces errors which limit overall system performance. One of the most important limitations is dynamic range, which is the range of signal amplitudes that can be captured by an ADC. This defines the minimum detectable signal in the presence of a larger, interfering signal. This is set both by the number of bits and the Signal to Noise Ratio (SNR). This article describes the use of a high speed, 16-bit ADC for weather radar signal capture. A simplified block diagram for this system is shown in Figure 1. A 16-bit ADC is used to capture the (C Band) transmit pulse after down conversion to IF. This adequately records the start pulse for synchronization and associated signal phase for demodulation. However, the input RF return signal has a dynamic range of 105 dB, which is greater than the (ideal theoretical) dynamic range for any commercial, high-speed ADC (limited to 16 bits). This dynamic range requires a 20-bit ADC as shown. To provide this capability, the normal input signal range is extended using instantaneous automatic gain control (AGC) as part of the digital signal processing (DSP) function. An ideal ADC has an SNR equal to 6.02 × N + 1.76 dB, where N is equal to the number of bits. For a 16-bit converter , this translates to 98 dB, which is the maximum (ideal theoretical) limit for input signal dynamic range. However, for high speed converters this ideal SNR is never achieved due to other issues which conspire to limit the SNR to a much lower value. These issues include ADC non-linearity, front end amplifier noise and sample clock jitter. A typical SNR value for a high-speed (120 MHz sample rate) ADC is about 76 dB, which is well below the theoretical limit. The ideal (98 dB) SNR is a comparison of the input noise level to a full scale input signal. In …